Quick Hits — September 4, 2026

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Quick Hits — September 4, 2026

A quick catch-up on the day's mid-tier AI stories — benchmark arguments, app-store politics, and a Chinese-lab capital plan that just broke cover.


ARC-AGI-3 reshapes the AGI timeline as Chollet concedes the pace is "twice as fast" as expected. ARC Prize ran GPT-6 Astra against its third-gen reasoning suite and, with its own harness, found the model cleared 96% of levels in fewer moves than the median human solver — about half the moves, on average. On a cost-per-game basis Astra came in roughly twice as efficient as the average human tester ($12.78 vs. Astra's fraction-of-a-cent equivalent). François Chollet used the results to publicly revise his AGI forecast: "Sooner, because progress is happening faster than I expected." ARC Prize is already building ARC-AGI-4 with a Q1 2027 release target.


Chinese app stores are reportedly floating a "double-authorization" rule that could lock AI agents out of mobile apps. Sina reports that major Chinese app stores are drafting a dual-consent requirement — the AI agent and the host app would both have to approve every interaction before an agent could read or tap a screen. It's the agent equivalent of Apple's App Tracking Transparency, and critics argue it would create a walled garden that only the largest platforms could negotiate through. Smaller developers and Western agents would effectively be cut off from China's mobile surfaces.


Moonshot is preparing a Hong Kong IPO that could raise $3B–$5B as soon as this year, Bloomberg sources say. The Kimi maker is weighing a listing on the Hong Kong exchange, with a target raise in the $3 billion to $5 billion range and a window that opens in the back half of 2026. The move would extend China's 2026 AI capital wave beyond Zhipu and DeepSeek and put Moonshot on a path toward the same "tier-one" funding tier as its domestic peers — though sources cautioned the size and timing are still preliminary.

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AI 101 — What is a chiplet?

AI 101 — What is a chiplet?

A chiplet is a piece of a processor that is manufactured as its own small chip, then packaged alongside other small chips so that the finished part behaves like one big chip. Instead of printing one enormous processor, you print several modest ones and wire them together inside a single package. Every flagship AI accelerator shipping today is built this way. It matters right now because the constraint on AI hardware has moved. TSMC's latest quarter put high-performance computing at 68% of plat

Jev 1.14.0 can read images — if you open its 'Danger Zone'

Jev 1.14.0 can read images — if you open its 'Danger Zone'

TypeSafe's decision model learned to look at pictures this morning, but the company shipped the capability behind a warning label instead of a launch announcement. Jev 1.14.0 adds image input, a new question type called Box, and a 262,000-token context window — all three shipped as experimental features behind a program TypeSafe calls the "Danger Zone." The features are off by default and have to be enabled per request through the API; TypeSafe's own documentation says they do not meet product

TSMC's sixth straight record quarter — 58.7% margin, 68% from HPC

TSMC's sixth straight record quarter — 58.7% margin, 68% from HPC

The chip cycle's upstream end and its downstream end told two different stories on the same morning: TSMC booked a sixth consecutive record, while the lab that buys its wafers told investors its growth rate is falling fast. TSMC's third-quarter net profit rose 68.7% to NT$763.1 billion (about $23.9 billion), a sixth consecutive record, on revenue of NT$1.494 trillion — up 50.9% year over year and roughly $46.7 billion. Both lines beat the LSEG SmartEstimate consensus (NT$1.46 trillion revenue,

Huawei ships its first logic-folded chip — and bonding is the gate

Huawei ships its first logic-folded chip — and bonding is the gate

Huawei has started mass production on a phone chip that engineers its way around the lithography wall instead of through it, and in doing so it has quietly moved the competitive bottleneck from transistor density to how tightly two silicon wafers can be glued together. Huawei's Kirin 9050 Pro is the first mass-produced logic-folding chip, stacking multiple dies and wiring them with more than 50 million hybrid bonds. The design puts circuits that would normally route sideways on a flat plane in