Samsung puts HBM base dies on a logic node to reclaim bandwidth
The memory stack feeding AI accelerators is getting a quiet overhaul. At Hot Chips 2026, Samsung laid out its plan to build High Bandwidth Memory base dies on a logic process node — a step change that frees up die area it wants to fill with memory controllers, sensors, and eventually compute.
Samsung revealed it now fabricates its HBM4 and HBM4E base dies on a 4nm logic node, breaking with the long-running practice of building them on a DRAM process. The move is a direct answer to the memory wall that is throttling AI training and inference: each HBM generation improves power efficiency, yet memory power keeps climbing, and the physical interface between the base die and the host chip already consumes most of the base die's area. A logic node curbs that power growth and, crucially, frees up enough spare die area that Samsung can no longer shrink the die (its footprint is set by the DRAM dies stacked above) — so it intends to put the space to work.
The talk laid out a three-phase roadmap. Phase one targets moving the memory controller onto the HBM base die, replacing the standard HBM host interface with a custom die-to-die link and reclaiming PHY area as effectively free space for the controller — a design that could let HBM talk to a compute chip directly, the same way Intel's Sapphire Rapids stack works. Phase two wants to add sensors for temperature and voltage telemetry, an on-die test block that works without a host, external memory interfaces to push capacity past interposer limits, and even in-memory compute for preprocessing data on the die. Phase three gets deliberately aggressive: stacking HBM dies directly on top of a compute chip, package-on-package style, an approach Samsung calls zHBM that promises big power and area savings but faces obvious thermal hurdles — AMD spent multiple Zen generations just taming 3D cache stacking thermals.
Samsung's near-term goals look achievable, and on-die test and RAS (reliability) features would need no special support from an attached compute die. The far-term ideas are a longer shot: they depend on compute-makers accepting custom HBM, which would force other DRAM vendors onto Samsung's private protocols in a multi-sourced supply chain. Still, this is the clearest signal yet that HBM — the component quietly responsible for much of an accelerator's real-world throughput — is becoming a far more active participant in compute rather than a passive memory block.
What to watch: whether the industry rallies around a standardized die-to-die protocol after Samsung's move, or fragments into vendor-specific designs.
Do you think the push to put logic and compute inside the memory stack changes the economics of AI hardware — or is it over-engineered? Tell us in the comments.
