DeepX DX-M2: 100B-parameter models at 5W, for under $50 a chip

Edge inference just got a lower floor on power and price — and the number that decides whether it works is not the TOPS figure.

DEEPX has taped out DX-M2, a single-die edge AI chip built on Samsung's 2nm process that the Korean fabless startup says will run 20-billion to 100-billion-parameter models at 10 to 30 tokens per second inside a 5-watt budget, at a target price under $50 a chip. The tapeout was completed and announced this month, with samples due in March 2027 and mass production targeted for fall 2027, as EE Times reported. That price is roughly a quarter of what Qualcomm's edge accelerators are said to cost per part, according to ZDNet Korea. If it holds, it changes the bill of materials for every battery-powered robot, drone and smart camera that currently has to choose between a cheap chip that cannot hold a useful model and an expensive one that can.

What the tapeout actually says

The spec sheet, published by DEEPX, is unusually specific for a pre-silicon part: 80 TOPS on the NPU, a single die in a 17×17mm flip-chip BGA package, and up to 96 GB of external LPDDR5X across four 24 GB packages on an eight-channel interface running at 153.6 GB/s. That is roughly triple the 50 GB/s of the first-generation DX-M1, and it is the figure that matters most. DEEPX's own chief executive, Kim Lokwon, told EE Times the single biggest change between generations is the memory bandwidth, not the compute.

There are three SKUs, and the power numbers differ in a way that is easy to misread. The flagship DX-M2 quotes about 5 W for the system-on-chip alone, with DRAM outside that budget. The DX-M2M puts 24 GB of DRAM in the package and draws 5 W total — 3 W for the SoC, 2 W for memory — with a narrower four-channel, 76.8 GB/s interface. The DX-M2M Pro carries 48 GB at 8.5 W. The 80 TOPS figure also comes with no stated numeric precision in any of the material published so far, so treat it as a headline rather than a comparable benchmark.

The 100-billion-parameter claim is a mixture-of-experts claim

The obvious objection to "100B parameters at 5 watts" is that no edge chip can hold a 100-billion-parameter model. It cannot, and DEEPX is not claiming it does. The stated capability is 20B to 100B total parameters with roughly 3B to 20B active per token, which is the signature of a sparse mixture-of-experts model: most of the weights sit idle, and only a slice is read for each token. Weights stream from the 96 GB of LPDDR5X, and decoding is bound by how fast that memory can feed the NPU, not by the arithmetic units.

The bandwidth arithmetic backs the tokens-per-second range and also caps it. At 153.6 GB/s, 20 tokens per second allows roughly 7.7 GB of weights to be streamed per token; at 10 tokens per second, about 15 GB. A 4-bit slice of a 3B-active model is comfortably inside that; a 20B-active slice at the same precision is at the edge of it. So the honest reading is a chip that can hold a very large MoE model's full weight set in mobile DRAM and decode a small active path at conversational speed — usable for a robot that needs to reason locally, not for anything that needs to be fast. That arithmetic is ours, not the vendor's, and the on-silicon numbers are still a year away.

The real technical bet is compute inside the DRAM

The more interesting part of the announcement is the memory itself. Samsung is supplying a custom LPDDR5X-PIM part — processing-in-memory, where some multiply-accumulate work happens inside the DRAM die instead of being shuttled across the bus. DEEPX's simulation puts the gain at 6.7× the tokens per second of DX-M2 alone on Llama 3.1 8B, at 2.7× the power, and the company thinks a 2× uplift is achievable inside the same envelope. That is a simulation of an offload strategy, not a measurement, and it should be read that way.

What gives it weight is the standards position. DEEPX and Qualcomm are the only two logic companies participating in the JEDEC work on LPDDR6-PIM, according to ZDNet Korea, and DEEPX's roadmap puts full LPDDR6-PIM — with 1 ePOPS of INT8 throughput on a chiplet-based DX-M3 — in 2028. PIM is one of the few remaining ways to widen an edge chip's effective bandwidth without widening the bus or raising the power, and the fact that a small Korean fabless company is in the room with Qualcomm on it is more consequential than any single TOPS figure in the brochure.

What DEEPX has that most edge-chip startups do not: shipping silicon

The credibility problem for edge accelerators is that the category is littered with announced parts that never reached volume. DEEPX has a first generation in mass production, more than 100 purchase orders for DX-M1, and a named customer of real weight — Hyundai Motor Group's robotics lab. It also has ecosystem work that matters more than benchmarks: integration with Intel's OpenVINO, talks with AMD on Kria, Raspberry Pi support, Baidu's PaddlePaddle, AWS IoT Greengrass, 17 software libraries, and DX-Newton, a homegrown substitute for Nvidia's Isaac robotics stack.

That software layer is the actual competitive question. Robotics teams prototyping today on Nvidia hardware are not paying for TOPS, they are paying for the toolchain, and a cheap part with a thin runtime is a false economy. DEEPX claims a switch away from Nvidia yields 20× longer battery life, but that figure comes from an M1-based demonstration with no published metric behind it — the kind of number that should be quoted only with the caveat attached. Our own coverage of compute-in-memory parts and d-Matrix stacking DRAM on its chip for 100 TB/s makes the same point: the memory interface is where the honest gains live, and vendor graphs are where they get overstated.

The counter-case

Everything above is pre-silicon. DEEPX's own product page still describes DX-M2 as in development, and its brochure carries the standard warning that specifications may change. There is no named DX-M2 customer or design win in any source published so far. The sub-$50 price was set in June, before tapeout, and has not been restated since — and 2nm wafer pricing from Samsung is the obvious pressure point on that number, which the company has not addressed publicly. The 100B framing is a mixture-of-experts total, not a dense model, and the 5 W figure excludes DRAM on the flagship part.

None of that makes the story small; it makes it a 2027 story. The part that will ship first, at scale, is the module with 24 GB of in-package memory at 5 W total, and that is the configuration robotics integrators should be evaluating for the next design cycle.

What to watch

March 2027, when the first samples go out and the token-rate claims meet a stopwatch. Whether the $50 target survives contact with 2nm wafer costs. Whether PIM arrives in DX-M2 silicon or waits for DX-M3 in 2028. And whether a robot maker puts its name on a design win, which is the only validation that outlasts a press release. For readers tracking the on-device model thread, our piece on Microsoft's Project Zenith running 30B models on dev PCs covers the other end of the same curve.

Would you put a 100-billion-parameter model in a robot at 10 tokens per second, or is that the wrong trade for real-time control? Write to us via our contact page.