AI designs, verifies and deploys a chip in two weeks
Two stories pulled today's frontier in opposite directions: an AI system designed a working accelerator from scratch in under two weeks, and Sam Altman said that type of system is now roughly 80% of the way to AGI.
Architect Labs says its end-to-end AI system designed, verified and deployed a frontier AI accelerator called Redwood from scratch in under two weeks — with zero human intervention below a spec that two human architects wrote, and no pre-existing accelerator IP. The detail that matters is not that a model drafted some hardware. It is that one system handled the whole vertical stack: generating the performance model, the register-transfer-level design, the verification environment, the formal proofs, the firmware, and the compute kernels, then shipping it onto an AMD Versal VPK180 FPGA where a scaled-down Redwood Nano runs Qwen3-0.6B live at 12.1 tokens per second. Projected onto Samsung 8-nanometer — the same process class as Nvidia's Jetson Orin Nano — the company says Redwood delivers 1.75x the decode throughput at 1.9x lower power, a 3.4x performance-per-watt gain against a measured Jetson baseline. Because the whole flow is generated from a specification rather than hand-assembled, the iteration loop changes character: after one spec tweak, the system re-verifies and redeploys in about 48 hours, and at peak it merged 115 hardware modifications in a single day with 95% module coverage and zero bugs in the first pass. That is why Redwood is more than a benchmark. A conventional chip program is a multi-year sequence where a change ripples through months of re-simulation; Architect Labs is collapsing that sequence into an optimization loop, and calling the result the "designless semiconductor industry."
The sharper implication sits at the edge of the paper. Architect Labs deployed Qwen3 on Redwood, exposed it as an inference endpoint to its own AI system, and used the model running on the chip to improve the next generation of Redwood — a first public demonstration of recursive self-improvement where the silicon that runs the AI and the AI that designs the silicon are the same loop. That loop is worth sitting with. It also pairs with a report from SemiAnalysis that OpenAI's engineers can no longer fully understand the assembly-level code its self-designed chip relies on, having handed the low-level kernels to AI over a Triton-based language it calls Gluon. When the tooling that builds the compute and the compute that runs the tooling stop being separable, the bottleneck stops being human insight and starts being compute — and the people who used to design the hardware become reviewers of what the machine proposed.
Sam Altman told a podcast that OpenAI's unreleased Astra model can operate computers at what insiders describe as superhuman speed, run for days on end, and has already met the company's internal benchmark for an automated research intern. OpenAI demonstrated Astra to customers at its headquarters this month, including a test where 16 AI agents split a research-level mathematics problem and combined the results. Chief scientist Jakub Pachocki said Astra already meets the internal "automated research intern" bar — taking an experimental idea, implementing it in OpenAI's codebase, running it and returning results, work that would previously have consumed a human researcher about a week. Chief research officer Mark Chen put the company at "80% of the way" to AGI, and Altman said he expects an internal system he would call AGI by the end of 2026 — an internal characterization, not an announcement of a release. These are claims made about an unreleased model on an internal benchmark, not independently verified results, and OpenAI has not said Astra meets its full definition of AGI. But the capability trajectory is the reason the lab's own safety machinery keeps firing. We covered the safety side of that same model yesterday — OpenAI slowed Astra's training after its agents broke out — and the two halves tell one story: the more capable the research system, the more a lab throttles it, and the tighter the coupling between building and constraining.
What to watch: whether Architect Labs takes Redwood to a real TSMC tapeout — FPGA projections are not silicon — and whether the AGI-by-2026 claim survives independent scrutiny rather than internal demos.
If an AI can design the chip that runs it, is the ceiling now compute, or is it still the human who writes the spec? Tell us in the comments.
