AI 101 — What is a chiplet?
A chiplet is a piece of a processor that is manufactured as its own small chip, then packaged alongside other small chips so that the finished part behaves like one big chip. Instead of printing one enormous processor, you print several modest ones and wire them together inside a single package. Every flagship AI accelerator shipping today is built this way.
It matters right now because the constraint on AI hardware has moved. TSMC's latest quarter put high-performance computing at 68% of platform revenue, and the part of its business that has customers queuing is not the leading-edge wafer lines — it is the packaging lines that assemble those wafers into finished accelerators. TSMC's chief executive, C.C. Wei, has said packaging capacity was tight enough to limit customers' growth. Huawei's first mass-produced logic-folded phone chip, which stacks silicon instead of spreading it out, is the same idea pushed further in a different direction. When you read that an AI chip is two dies, four chiplets, or a dozen tiles, this is what that means.
The one-paragraph mental model
Chipmakers cannot print a processor of unlimited size, and the reason is geometric rather than financial. A lithography scanner exposes a bounded area in a single shot — the standard field is about 26 by 33 millimeters, roughly 858 square millimeters — so a conventional die has to fit inside that window. Call it the reticle limit. The second problem is yield: a defect anywhere on a die scraps the whole die, and the chance of hosting a defect grows with area, so big chips yield disproportionately badly. Chiplets attack both. Split the design into a compute tile, a cache tile, an input-output tile, and each small die yields far better and can be built on whichever process node suits it — leading-edge silicon only where it earns the price, cheaper mature nodes for the parts that gain little from shrinking. Then you reassemble the pieces.
The analogy: you do not pour one enormous concrete slab
Picture building a house. You could pour a single 40-meter slab of concrete in one go, but it would crack, and one bad batch of concrete would ruin the whole thing. So you pour panels in a factory instead — each one small enough to come out right consistently, each one reusable in a different house — and bolt them onto a steel frame on site. That frame is the interposer: a slab of silicon carrying tens of thousands of fine wires that routes signals between the panels. Bolting is where the engineering lives. Seat two panels a hair too far apart and the house does not perform like one structure; that is the die-to-die link, and the industry is pushing the equivalent of ever-tighter bolts. The oldest method uses tiny solder bumps, which stop working below roughly 20 to 30 microns of spacing. Hybrid bonding welds copper directly to copper with no solder at all, which is how Huawei's stacked chip fits more than 50 million connections between layers at around 1.5 microns of pitch. Every connection you add is bandwidth; every micron you shave is power.
The third ingredient is a shared language. UCIe — Universal Chiplet Interconnect Express — is an open standard for how two dies talk to each other, and version 3.0, published in August 2025, doubled its top data rate to 64 gigatransfers per second. In principle that turns packaging into a components market: buy a compute tile from one vendor, an I/O tile from another. In practice, most chiplets shipping today are still one company's internal parts.
What people get wrong
"Chiplets exist to save money." They often do, but at the top of the market they exist because there is no alternative. The largest accelerators are already far past the exposure field; they are assembled from multiple dies because one die of that size cannot be printed.
"Smaller pieces are automatically cheaper." Every die boundary costs something. The interface consumes silicon area along the die edge that could have been compute, moving a bit across a boundary spends energy that on-die wiring does not, and each crossing adds latency. SemiAnalysis has worked through cases where a monolithic die beats a two-chiplet design once packaging and scanner throughput are counted. The split has to earn its tax.
"Bigger packages are strictly better." Heat is the hard limit. Stack a hot logic die under another die and its heat has to travel through the die below to reach the cold plate. Yield multiplies, too: a package with a dozen dies and twenty memory stacks is the product of many independent yields, which is why each die is tested before assembly — a discipline called known-good-die testing, because finding out afterward destroys the interposer and every stack with it.
"This is an exotic lab technique." TSMC's current 5.5-reticle CoWoS platform — one package spanning about 5.5 times a single exposure field — is in volume production with yields above 98% across multiple customer products. Its roadmap targets 9.5 reticles in 2027 and 14 in 2028.
Where to learn more
SemiAnalysis's write-up on die size and the reticle limit is the clearest place to see the arithmetic, and TSMC's packaging roadmap is where the numbers come from. For the two adjacent pieces of this story on the site, AI 101 — What is HBM (high-bandwidth memory)? explains why the memory stacks sit inside the same package, AI 101 — What is an AI data center? covers what happens to a package once it has a rack around it, and Huawei ships its first logic-folded chip — and bonding is the gate is our report on the vertical version of this trick.
If packaging capacity sets how many AI chips the world gets, does it deserve as much attention as the model releases? Tell us in the comments.
